Zarlink's New Single-Chip TDM-to-IP/Ethernet Packet Processors Deliver Industry's Highest Capacity, Best Performance

Zarlink's devices are the only packet processors capable of sending high volumes of TDM traffic - up to 32 T1/E1 streams - over IP/Ethernet networks with the same voice quality and service flexibility as conventional, TDM-based telephone networks. With the unmatched features of the three-chip, standards- compliant ZL50111 family, designers can significantly improve the performance of TDM-to-IP/Ethernet access systems, while cutting cost, size, and power consumption.

"Our second-generation packet processors deliver the industry's most advanced and cost-effective method of circuit-to-packet conversion and transmission - an emerging capability known as Circuit Emulation Services over Packet, or CESoP," said Jitesh Vadhia, senior vice president and general manager, Network Communications, Zarlink Semiconductor. "The key to this achievement is the first-ever integration of two critical voice/data convergence functions - network timing and synchronization, and packet processing - in a single device."

Described by Zarlink's lead customers as an "enabling technology" for the adoption of IP/Ethernet technology in metro networks, global equipment vendors are already designing Zarlink's ZL50111 devices into equipment such as routers, switches, IADs (integrated access devices), wireless backhaul systems, and Ethernet passive optical network systems.

Expanding equipment market

To handle the rising volumes of IP data traffic, service providers are stepping up investments in metro Ethernet packet networks, which commonly feature high-speed IP/Ethernet links to customer sites. As a result, demand is growing for a new class of network edge equipment with TDM-to-IP/Ethernet conversion capabilities, or CESoP. This equipment lowers costs by allowing less expensive Ethernet networks to carry high quality, profitable TDM services, such as T1/E1 leased lines.

Carrier-class voice quality

A key challenge in delivering CESoP is achieving the precise levels of network synchronization and clocking required to reliably deliver constant bit- rate voice traffic over variable bit-rate packet networks. Zarlink has met this goal by implementing more than 15 patent-pending hardware and software processing techniques that allow the ZL50111 family to deliver carrier-class voice quality in both adaptive and differential synchronization modes.

Voice quality is also enhanced by advanced on-chip QoS mechanisms, such as weighted fair queuing and strict priority. These mechanisms help minimize the effects of network latency, or end-to-end packet transit time, by giving time-sensitive voice packets priority over data packets in processing queues.

"Our devices use innovative processing algorithms to perform complex TDM clock recovery functions on-chip - a world first," said Bruce Ernhofer, product manager, Packet Processors, Zarlink Semiconductor. "This capability, combined with priority queuing, allows the chips to consistently meet the industry's stringent QoS criteria for voice transport."

Extensive range of traffic densities

Zarlink's family of TDM-to-IP/Ethernet packet processors consists of three chips that allow equipment manufacturers to cost-effectively support a wide range of TDM traffic densities and data rates. The ZL50111 device provides CESoP for 32 T1/E1 ports, or 1024 64-Kb/s (kilobit per second) channels. By contrast, CESoP chips from other vendors support only one T1/E1 port. Two of the ports on the ZL50111 can also be configured to deliver high- speed T3/E3 services operating at 45 Mb/s.

The ZL50110 chip processes eight T1/E1 ports, or 256 64-Kb/s channels, while the ZL50114 device supports four T1/E1 ports, or 128 channels. All three chips support a broad array of TDM traffic formats, including unstructured mode, structured mode, and fractional N x 64 Kb/s mode.

Single-chip processors deliver service flexibility

To enhance service flexibility, all TDM ports on Zarlink's new packet processors are equipped with their own DCO (digitally controlled oscillator). The DCOs allow each TDM port to be synchronized to a reference clock, which in turn lets services be routed on a per-port basis. Traffic on some TDM ports, for example, can be sent via Ethernet to the PSTN (public switched telephone network), while services on other ports can be Ethernet-routed to different locations, bypassing the PSTN.

Zarlink's new packet processors deliver this service flexibility without using external memory devices. The chips feature on-chip SRAM (static random access memory) circuitry with enough capacity to buffer data in 32 T1/E1 ports for 16 ms (milliseconds). This is more than ample for most metro Ethernet networks, which typically have latencies, or end-to-end data transport times, of no more than 5 ms.

Standards compliance

Zarlink's ZL50111 family of processors complies with the ITU-T's (International Telecommunication Union-Telecommunications) G.823 and G.824 traffic interface specifications for jitter and wander control in T1/E1 networks. The chips also comply with draft standards for native TDM circuit emulation proposed by the IETF's (Internet Engineering Task Force) PWE3 (Pseudo Wire Emulation edge-to-edge) working group.

Pricing and availability

The ZL50111 packet processors are now in production. A complete reference design, an evaluation board, and a software API (application programming interface) support the devices. All three are offered in 552-pin PBGA (plastic ball grid array) packages. In quantities of 1,000, the ZL50111 is priced at US$276.47, the ZL50110 at US$181.18, and the ZL50114 at US$129.41.

For more information about the ZL50111 family and CESoP, please visit http://cesop.zarlink.com/.

About Zarlink Semiconductor

For almost 30 years, Zarlink Semiconductor has delivered semiconductor solutions that drive the capabilities of voice, enterprise, broadband and wireless communications. The company's success is built on its technology strengths, including voice and data networks, consumer and ultra low-power communications, and high-performance analog. For more information, visit http://www.zarlink.com/.

Certain statements in this press release constitute forward-looking statements within the meaning of the Private Securities Litigation Reform Act of 1995. Such forward-looking statements involve known and unknown risks, uncertainties, and other factors which may cause the actual results, performance or achievements of the Company to be materially different from any future results, performance, or achievements expressed or implied by such forward-looking statements. Such risks, uncertainties and assumptions include, among others, the risks discussed in documents filed by the Company with the Securities and Exchange Commission. Investors are encouraged to consider the risks detailed in those filings.

A high-resolution photograph is available at http://news.zarlink.com/visual_center/. Zarlink, ZL, and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

FACT FILE

This file accompanies the news release issued September 16, 2003 and titled "Zarlink Unveils Breakthrough High-Capacity Packet Processors."

Circuit Emulation Services over Packet (CESoP): A new voice/data conversion technology that allows packet-switched networks to transport conventional, TDM circuit-switched voice and data traffic with no loss in QoS (quality of service).

Circuit-switched networking: The technique used in traditional public- switched telephone networks (PSTN) to transmit voice and data. Using switches, a dedicated physical circuit path is set up between two network end-points. Voice or data is transmitted in a synchronized, constant bit-rate stream, usually 64-Kb/s (kilobits per second), over the circuit path for the duration of the call. During that time, no one else can use the circuit path. Circuit switching provides excellent QoS for time-sensitive traffic such as voice and video.

Time-division multiplexing (TDM): A digital time-interleaving technique for transporting multiple 64-Kb/s circuit-switched voice or data streams over one copper or fiber cable.

T1/E1: The predominant TDM standards for access networks. About 85% of Fortune 500 companies use T1/E1 trunks to connect to central offices. T1, used primarily in North America, combines 24 64-Kb/s channels into one 1.544 Mb/s (megabits per second) stream. E1, used primarily in Europe, combines 32 64- Kb/s channels into one 2.048 Mb/s stream.

Packet-switched networking: The technique used in local- and wide-area networks (LANs/WANs) to transmit Internet Protocol (IP) and other data traffic between two points. Data is divided into variable-sized pieces called packets. The packets are transmitted individually to the destination point. Once all the packets arrive, they are reassembled into the original data message. Packets from different data messages often share the same physical network path, allowing for efficient use of bandwidth.

Ethernet: As the dominant global LAN protocol, Ethernet is quickly expanding into metro networks to carry growing levels of IP access traffic. Ethernet is part of the seven-layer protocol stack defined in the OSI Reference Model for networks carrying IP-based data. Ethernet operates at Layer 2, the "data link" layer of the stack.

Packet processor: A new class of integrated circuit that uses highly efficient processing techniques to convert TDM voice and data traffic to packets for transport over IP/Ethernet networks. Advanced packet processing chips, such as Zarlink's ZL50111 family, provide on-chip packetization of both the voice stream and the network timing information needed to deliver the voice stream with high QoS. Less advanced chips require external circuitry to packetize timing information.

CONTACT: Zarlink, Michael Salter, Media Relations,
613 270-7115, michael.salter@zarlink.com; United States, Natalie Sauve,
High Road Communications, 613 236-0909, nsauve@highroad.com; Europe, June
Stokes, Pinnacle Marketing Communications, 44 (0) 1270-879205,
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